Semiconductor structure and manufacturing method thereof, memory chip and electronic device

ABSTRACT

A semiconductor structure comprises a substrate, wherein the substrate is provided with a stacked structure, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, the stacked structure further comprising a plurality of horizontal signal lines arranged in the second direction, wherein each of the horizontal signal lines is in contact with one layer of the memory cells; and a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation of International Patent Application No.PCT/CN2022/109526, filed on Aug. 1, 2022, which claims priority toChinese Patent Application No. 202210709274.2, filed on Jun. 21, 2022.The disclosures of International Patent Application No.PCT/CN2022/109526 and Chinese Patent Application No. 202210709274.2 arehereby incorporated by reference in their entireties.

BACKGROUND

A semiconductor structure includes a plurality of memory cells, and thememory cells need to be connected to a peripheral circuit to execute astorage function. The higher the integration level of the semiconductorstructure is, the greater the number of the memory cells capable ofbeing accommodated in the semiconductor structure is, and the moreexcellent the performance of the semiconductor structure is. However,many spaces in the current semiconductor structure are wasted. Further,due to the limitation from physical properties, the volume of the memorycell has reached the scaling limit, and due to the limitation fromprocess factors, it is also difficult to increase the number of stackedlayers of the memory cell.

Therefore, it is an urgent need of a semiconductor structure with a newarchitecture to improve the integration level of the semiconductorstructure.

SUMMARY

Embodiments of the disclosure belong to the field of semiconductors, andprovide a semiconductor structure and a manufacturing method thereof, amemory chip and an electronic device, which at least contributes toimproving the integration level of the semiconductor structure.

According to some embodiments of the disclosure, on the one hand, theembodiments of the disclosure provide a semiconductor structure. Thesemiconductor structure includes: a substrate, on which a stackedstructure is provided, where the stacked structure includes a pluralityof memory cell groups arranged in a first direction, each of the memorycell groups including multiple layers of memory cells arranged in asecond direction, and the stacked structure further includes a pluralityof horizontal signal lines arranged in the second direction, and each ofthe horizontal signal lines is in contact with one layer of the memorycells; and a plurality of leading wire posts arranged in the firstdirection, where the plurality of leading wire posts and the pluralityof horizontal signal lines are arranged along a third direction, and theleading wire posts are contacted with the horizontal signal lines.

According to some embodiments of the disclosure, on the other hand, theembodiments of the disclosure provide a semiconductor structure. Thesemiconductor structure includes: a substrate, on which a stackedstructure is provided, where the stacked structure includes a pluralityof memory cell groups arranged in a first direction, each of the memorycell groups including multiple layers of memory cells arranged in asecond direction, and the stacked structure further includes a pluralityof horizontal signal lines arranged in the second direction, where eachof the horizontal signal lines is in contact with one layer of thememory cells; and a plurality of leading wire posts arranged in thefirst direction and extending along the second direction, whereorthographic projections of the plurality of leading wire posts on thesurface of the substrate and orthographic projections of the horizontalsignal lines on the surface of the substrate are at least partiallyoverlapped, and the leading wire posts are contacted with the horizontalsignal lines.

According to some embodiments of the disclosure, on the other hand, theembodiments of the disclosure provide a method for manufacturing asemiconductor structure. The method includes the following operations. Asubstrate is provided. A stacked structure is formed on the substrate.The stacked structure includes a plurality of memory cell groupsarranged in a first direction, each of the memory cell groups includingmultiple layers of memory cells arranged in a second direction, and thestacked structure further includes a plurality of horizontal signallines arranged in the second direction, where each of the horizontalsignal lines is in contact with one layer of the memory cells. Aplurality of leading wire posts arranged in the first direction isformed. The plurality of leading wire posts and the plurality ofhorizontal signal lines are arranged along a third direction, and theleading wire posts are contacted with the horizontal signal lines.

According to some embodiments of the disclosure, on the other hand, theembodiments of the disclosure provide a method for manufacturing asemiconductor structure. The method includes the following operations. Asubstrate is provided. A stacked structure is formed on the substrate.The stacked structure includes a plurality of memory cell groupsarranged in a first direction, each of the memory cell groups includingmultiple layers of memory cells arranged in a second direction, and thestacked structure further includes a plurality of horizontal signallines arranged in the second direction, where each of the horizontalsignal lines is in contact with one layer of the memory cells. Aplurality of leading wire posts arranged in the first direction andextending along the second direction is formed, where orthographicprojections of the plurality of leading wire posts on the surface of thesubstrate and orthographic projections of the horizontal signal lines onthe surface of the substrate are at least partially overlapped, and theleading wire posts are contacted with the horizontal signal lines.

According to some embodiments of the disclosure, the embodiments of thedisclosure further provide a memory chip. The memory chip includes theaforementioned semiconductor structures.

According to some embodiments of the disclosure, the embodiments of thedisclosure further provide an electronic device. The electronic deviceincludes the aforementioned memory chip.

Technical solutions provided by the embodiments of the disclosure atleast have the following advantages.

In some embodiments of the disclosure, the stacked structure includes aplurality of horizontal signal lines arranged in the second direction,each of the horizontal signal lines is contacted with one layer ofmemory cells in the stacked structure, the plurality of leading wireposts and the plurality of horizontal signal lines are arranged along athird direction, and the leading wire posts are contacted with thehorizontal signal lines. That is, in the third direction, the leadingwire posts are directly connected to the horizontal signal lines, sothat it contributes to reducing the number of staircases or it is nolonger to arrange a staircase area independently, thereby improving theintegration level of the semiconductor structure.

In some other embodiments of the disclosure, the plurality of leadingwire posts extend along the second direction, and orthographicprojections of the plurality of leading wire posts on the surface of thesubstrate and orthographic projections of the horizontal signal lines onthe surface of the substrate are at least partially overlapped. That is,the leading wire posts are directly connected to the horizontal signallines in an alternative manner, so that it contributes to reducing thenumber of staircases or it is no longer to arrange a staircase areaindependently, thereby improving the integration level of thesemiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments consistent with thedisclosure and, together with the description, serve to explain theprinciples of the disclosure. It is apparent that the accompanyingdrawings described below are merely some embodiments of the disclosure,and other drawings can be obtained by those of ordinary skill in the artaccording to these accompanying drawings without creative efforts.

FIG. 1 illustrates a top view of a semiconductor structure.

FIG. 2 illustrates a partial enlarged drawing of FIG. 1 .

FIG. 3 illustrates a section view of FIG. 2 in the direction A-A1.

FIG. 4 illustrates a stereogram of a semiconductor structure provided byan embodiment of the disclosure.

FIG. 5 illustrates a stereogram of another semiconductor structureprovided by an embodiment of the disclosure.

FIG. 6 illustrates a partial side view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 7 illustrates another partial side view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 8 illustrates another partial side view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 9 illustrates another partial side view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 10 illustrates another partial side view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 11 illustrates a partial section view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 12 illustrates another partial section view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 13 illustrates another partial section view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 14 illustrates a top view of a semiconductor structure provided byan embodiment of the disclosure.

FIG. 15 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 16 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 17 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 18 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 19 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 20 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 21 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 22 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 23 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 24 illustrates another partial section view of a semiconductorstructure provided by an embodiment of the disclosure.

FIG. 25 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 26 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 27 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 28 illustrates another top view of a semiconductor structureprovided by an embodiment of the disclosure.

FIG. 29 illustrates a stereogram of a semiconductor structure providedby another embodiment of the disclosure.

FIG. 30 illustrates a stereogram of another semiconductor structuresprovided by another embodiment of the disclosure.

FIG. 31 illustrates a section view of a semiconductor structure providedby another embodiment of the disclosure.

FIG. 32 illustrates another section view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 33 illustrates a partial enlarged drawing of FIG. 32 .

FIG. 34 illustrates another section view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 35 illustrates a partial enlarged drawing of FIG. 34 .

FIG. 36 illustrates another section view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 37 illustrates a partial enlarged drawing of FIG. 36 .

FIG. 38 illustrates a top view of a semiconductor structure provided byanother embodiment of the disclosure.

FIG. 39 illustrates another top view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 40 illustrates another top view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 41 illustrates another top view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 42 illustrates another top view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 43 illustrates another top view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 44 illustrates another top view of a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 45 illustrates a schematic structural diagram corresponding tooperations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 46 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 47 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 48 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 49 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 50 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 51 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 52 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 53 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 54 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 55 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 56 illustrates another schematic structural diagram correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 57 illustrates a schematic structural diagram corresponding tooperations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 58 illustrates another schematic structural diagrams correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 59 illustrates another schematic structural diagrams correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

FIG. 60 illustrates another schematic structural diagrams correspondingto operations of a method for manufacturing a semiconductor structureprovided by another embodiment of the disclosure.

DETAILED DESCRIPTION

FIG. 1 is a top view of a semiconductor structure. FIG. 2 is an enlargeddrawing of a staircase in a dotted circle in FIG. 1 . FIG. 3 is asection view of FIG. 2 in the direction A-A1. Referring to FIG. 1 toFIG. 3 , the semiconductor structure includes a memory cell area 100 anda staircase area 200. There are multiple layers of memory cells in thememory cell area 100. There are multiple staircases in the staircasearea 200, and the staircases and the memory cells are arranged inone-to-one correspondence. A connecting layer (not shown in the drawing)can be arranged in the staircase, a leading wire post 300 can bearranged on the staircase, and the leading wire post 300 areelectrically contacted with the memory cell through the connecting layerin the staircase, so as to lead out the memory cell, so that it isconvenient to connect the memory cell to a peripheral circuit. However,with increase of stacked layers of the memory cells, the area occupiedby the staircase area 200 will be larger and larger. For example, ifthere are totally 64 layers of memory cells, correspondingly, 64staircases are needed, and the lower the staircase is, the larger thearea is. If the area of the topmost staircase is 0.25 μm², the area ofthe bottommost staircase is 64*0.25=16 μm². Referring to FIG. 3 , theconnecting layer below each staircase only provides support and electricconnection, so that the bottom space is wasted. Therefore, theintegration level of the semiconductor structure needs to be furtherimproved.

The embodiments of the disclosure provide a semiconductor structure. Insuch semiconductor structure, the plurality of leading wire posts andthe plurality of horizontal signal lines are arranged along the thirddirection, and the leading wire posts and the horizontal signal linesare connected; alternatively, the plurality of leading wire posts extendalong the second direction, and orthographic projections of theplurality of leading wire posts on the surface of the substrate are atleast partially overlapped with orthographic projections of thehorizontal signal lines on the surface of the substrate. That is, theleading wire posts and the horizontal signal lines are directlyconnected in a parallel manner or an alternative manner. Therefore, itis unnecessary to connect the leading wire posts to the horizontalsignal lines through a connection layer in the staircase area, so thatthe space utilization ratio in the semiconductor structure is improved,thereby improving the integration level of the semiconductor structure.

The embodiments of the disclosure will be described below in detail incombination with the drawings. However, those of ordinary skill in theart may understand that many technical details are provided to betterunderstand the disclosure in the embodiments of the disclosure. However,the technical solutions claimed by the disclosure may also beimplemented even though there are no these technical details and variouschanges and modifications based on the following embodiments.

As shown in FIG. 4 -FIG. 28 , an embodiment of the disclosure provide asemiconductor structure. The semiconductor structure includes: asubstrate (not shown in the drawings), on which a stacked structure isprovided, the stacked structure includes a plurality of memory cellgroups TC0 arranged in the first direction X, and each of the memorycell groups TC0 includes multiple layers of memory cells TC arranged ina second direction Z, and the stacked structure further includes aplurality of horizontal signal lines 3 arranged in the second directionZ, and each of the horizontal signal lines 3 is contacted with one layerof the memory cells TC; and a plurality of leading wire posts 5 arrangedin a first direction X, the plurality of leading wire posts 5 and theplurality of horizontal signal lines 3 are arranged along a thirddirection Y, and the leading wire posts 5 are contacted with thehorizontal signal lines 3.

That is, the edge of the orthographic projection of the leading wirepost 5 on the surface of the substrate is in contact with the edge ofthe orthographic projection of the horizontal signal line 3 on thesurface of the substrate. In other words, at least part of side walls ofthe leading wire post 5 is directly contacted with a side wall of thehorizontal signal line 3, and it is unnecessary to connect indirectlythrough the connection layer of the staircase area, so that the numbersof the connection layers and the staircases may be decreased, therebyfacilitating to improve the integration level of the semiconductorstructure.

The semiconductor structure will be described below in detail incombination with the drawings.

It is to be noted first that FIG. 6 -FIG. 10 are partial top views. Fora more intuitive purpose, FIG. 6 -FIG. 9 do not illustrate a structurefor isolating and supporting the leading wire post 5 in thesemiconductor structure. FIG. 10 illustrates the structure for isolatingand supporting the leading wire post 5.

In some embodiments, referring to FIG. 6 -FIG. 10 , each horizontalsignal line 3 is at least contacted with one leading wire post 5. Thatis, each horizontal signal line 3 may be directly contacted with theleading wire post 5, so as to be led out by the leading wire post 5.Therefore, it may be unnecessary to arrange the staircase areaindependently, so that the space utilization ratio of the semiconductorstructure can be improved to a great extent, and it contributes tosimplifying the production process.

Exemplarily, referring to FIG. 6 -FIG. 8 , the plurality of horizontalsignal lines 3 are contacted with the plurality of leading wire posts 5in one-to-one correspondence. That is, each horizontal signal line 3 iscontacted with one leading wire post 5, so as to reduce the connectionpositions between the horizontal signal lines 3 and the leading wireposts 5, and make the production process simpler. In some otherembodiments, referring to FIG. 9 , one horizontal signal line 3 may alsobe contacted with the plurality of leading wire posts so that thecontact regions between the horizontal signal line 3 and the leadingwire posts may be increased, and the contact resistance is reduced.

In some embodiments, referring to FIG. 4 -FIG. 13 , the leading wireposts 5 extend along the second direction Z. That is, the plurality ofleading wire posts 5 are parallel one another, and the extensiondirections of the leading wire posts 5 are the same as the stackingdirection of the memory cells TC, which contributes to simplifying theprocess and improving the uniformity of the semiconductor structure.Exemplarily, the stacking direction of the memory cells TC is the seconddirection Z which is perpendicular to the surface of the substrate.

Referring to FIG. 4 -FIG. 11 , it is to be noted that with respect tothe leading wire post 5 contacted with the horizontal signal line 3 ofthe non-top layer, the leading wire post may be arranged adjacent tomultiple layers of horizontal signal lines 3. It may be known based on aleading function of the leading wire posts 5 that, each leading wirepost 5 is only connected to one horizontal signal line 3, rather thantwo horizontal signal lines 3 at the same time. Otherwise, signaldisturbance occurs. In order to facilitate understanding, the horizontalsignal line 3 connected to the leading wire post 5 is called as thehorizontal signal line 3 of the corresponding layer. The leading wirepost 5 is arranged to be insulated from horizontal signal lines 3,except the horizontal signal line 3 of the corresponding layer. Inaddition, the leading wire post 5 is divided into a contact portion 51and an extension portion 52 arranged in a stacked manner. The contactportion 51 and the horizontal signal line 3 of the corresponding layerare arranged in the same layer and are connect to each other. Theextension portion 52 is arranged adjacent to the horizontal signal line3 above the corresponding layer, but insulated from the horizontalsignal line.

Correspondingly, referring to FIG. 5 -FIG. 13 , the stacked structuremay further include a dielectric layer 6. The dielectric layer 6 is atleast located on a side wall of the leading wire post 5 facing thehorizontal signal line 3 above the corresponding layer, and the lowersurface of the dielectric layer 6 is higher than the horizontal signalline 3 connected to the leading wire post 5. That is, the dielectriclayer 6 is used for isolating the leading wire post 5 from thehorizontal signal lines 3 out of the corresponding layer, so as to avoidincorrect electrical connections. Specifically, the dielectric layer 6may encircle the side walls of the extension portion 52 of the leadingwire post 5. A material of the dielectric layer 6 may be a material witha low dielectric constant, such as silicon nitride or silicon oxide.

In some embodiments, referring to FIG. 4 -FIG. 10 , the leading wireposts 5 connected to different horizontal signal lines 3 are differentin length in the second direction Z, and the bottoms of the leading wireposts 5 are contacted with the horizontal signal lines 3. Exemplarily,the leading wire post 5 connected to the horizontal signal line 3 of thetop layer is the shortest in the second direction Z, and the leadingwire post 5 connected to the horizontal signal line 3 of the bottomlayer is the longest in the second direction Z, which contributes tosaving the material, so as to further reduce the production cost, andfurther contributes to simplifying the production process. In some otherembodiments, the leading wire posts 5 may be same in length, but theleading wire posts 5 are only connected to the horizontal signal lines 3of the corresponding layer and are arranged to be insulated from thehorizontal signal lines 3 above and below the corresponding layer.

In order to increase the contact region between the leading wire post 5and the horizontal signal line 3 to decrease the contact resistance, thebottom surface of the leading wire post 5 may be aligned with the bottomsurface of the horizontal signal line 3 of the corresponding layer;alternatively, the bottom surface of the leading wire post 5 may beslightly lower than the bottom surface of the horizontal signal line 3of the corresponding layer. In some other embodiments, the bottomsurface of the leading wire post 5 may be higher than the bottom surfaceof the horizontal signal line 3 of the corresponding layer, but lowerthan the top surface of the horizontal signal line 3 of thecorresponding layer.

In some embodiments, referring to FIG. 6 -FIG. 7 , the adjacent leadingwire posts are arranged at an equal spacing in the first direction X.That is, the spacing between the adjacent leading wire posts 5 is thesame, so that the uniformity of the semiconductor structure is improved.

Referring to FIG. 6 , the leading wire posts 5 may be arranged in theorder of the length magnitude in the second direction Z. In some otherembodiments, referring to FIG. 7 , the lengths of the leading wire posts5 may not be increased or decreased progressively but alternative inlength, so that a large parasitic capacitance is prevented from beinggenerated between the longer leading wire posts 5.

In some other embodiments, referring to FIG. 8 , a spacing between theadjacent leading wire posts 5 is in proportion to an area of a directlyfacing region. It is to be noted that the area of the directly facingregion between the adjacent leading wire posts 5 is in proportion to themagnitude of the parasitic capacitance. Therefore, in a case that thearea of the directly facing region between the adjacent leading wireposts 5 is large, the spacing between the leading wire posts may becorrespondingly increased to reduce the parasitic capacitance.

In some embodiments, referring to FIG. 10 -FIG. 12 , the stackedstructure further includes multiple etching barrier layers 13 arrangedin the second direction Z, and each etching barrier layer 13 iscontacted with a bottom surface of at least one leading wire postSpecifically, a method for forming the leading wire post 5 includes:forming a through hole 8 (referring to FIG. 53 ) in one side of thehorizontal signal line 3 by adopting an etching process, and depositinga conductive material in the through hole 8 to form the leading wirepost 5. Therefore, the position of the through hole 8 decides theposition of the leading wire post 5. The etching barrier layer 13 maystop etching to realize a self-aligning function, so as to avoid theproblem of over-etching or insufficient etching of the through hole 8.That is to say, the etching barrier layers 13 and isolation layers 14are alternatively arranged in the second direction Z, the etchingbarrier layer 13 directly faces a gap between the two adjacenthorizontal signal lines 3, the isolation layer 14 and the horizontalsignal line 3 are arranged in the same layer, and the etch selectivityratio of the isolation layer 14 to the etching barrier layer 13 islarge. Exemplarily, a material of the isolation layer 14 may be siliconoxide, and a material of the etching barrier layer 13 may be siliconnitride. In addition, the etching barrier layer 13 may also provide anisolating function.

In some other embodiments, referring to FIG. 13 , only the isolationlayer 14 may be arranged on one side of the horizontal signal line 3,and no etching barrier layer 13 is arranged. Correspondingly, in theprocess of forming the through hole 8, the depth of the through hole 8is controlled by means of an etching time. Therefore, only one etchingagent may be used, thereby simplifying the manufacturing process.

Referring to FIG. 4 -FIG. 5 and FIG. 11 -FIG. 28 , the memory cell TCincludes a channel region 22 and source/drain doped regions 21 arrangedin the third direction Y, and the source/drain doped regions 21 arelocated on two sides of the channel region 22. That is, the memory cellTC at least includes a transistor T. In some other embodiments, thememory cell TC may further include a capacitor C. The transistor T andthe capacitor C are arranged in the third direction Y. Exemplarily, in aDynamic Random Access Memory (DRAM), the memory cell TC includes atransistor T and a capacitor C. In some other embodiments, the memorycell TC may only include the transistor T. For example, in a StaticRandom-Access Memory (SRAM), the memory cell TC is composed of sixtransistors T. For another example, a Capacitorless Double Gate QuantumWell Single Transistor (1T DRAM), the memory cell TC is composed of onedual gate transistor T.

Referring to FIG. 4 -FIG. 5 , the stacked structure further includesperpendicular signal lines 4 extending along the second direction Z andcontacted with multiple layers of memory cells TC of the same memorycell group TC0. One of the horizontal signal line 3 and theperpendicular signal line 4 is a bit line (BL), and the other of thehorizontal signal line 3 and the perpendicular signal line 4 is a wordline (WL). The BL is contacted with the source/drain doped region 21,and the WL is contacted with the channel region 22. The source/draindoped region 21 contacted with the BL is called as the firstsource/drain doped region 211, and the source/drain doped region 21arranged spaced from the BL is called as the second source/drain dopedregion 212.

Position relationships between the horizontal signal lines 3 and theleading wire posts 5 will be described below in detail in twosituations: the horizontal signal lines are BLs and the horizontalsignal lines are WLs.

In a case that the horizontal signal lines 3 are BLs, the horizontalsignal lines 3 and the leading wire posts 5 mainly have the followingseveral position relationships.

In example 1, referring to FIG. 14 -FIG. 18 , the leading wire post 5and the memory cell TC are respectively located on two opposite sides ofthe horizontal signal line 3 arranged in the third direction Y, that is,the leading wire post 5 is located on the side of the horizontal signalline 3 away from the memory cell TC. Therefore, it may be more flexibleto set arrangement positions and dimensions of the leading wire posts 5.

Specifically, referring to FIG. 14 , in some embodiments, the leadingwire post 5 directly faces the memory cell group TC0 in the thirddirection Y, which contributes to improving the uniformity of positionarrangement. In some other embodiments, referring to FIG. 15 , theleading wire posts 5 and the memory cell groups TC0 are arrangedalternatively in the first direction X, that is, the leading wire post 5directly faces the space between adjacent memory cell groups TC0. Insome other embodiments, referring to FIG. 16 , the leading wire post 5is arranged simultaneously opposite the memory cell group TC0 and thespace between the adjacent memory cell groups TC0. In some otherembodiments, referring to FIG. 17 , a part of leading wire posts 5directly faces the space between adjacent memory cells TC0, and part ofleading wire posts 5 directly faces the memory cell group TC0.

Continuously referring to FIG. 14 -FIG. 17 , in order to reduce theparasitic capacitance between the adjacent leading wire posts 5, the gapbetween the adjacent leading wire posts 5 may be arranged opposite atleast one memory cell group TC0. In addition, referring to FIG. 14 -FIG.16 , in order to increase the uniformity of the semiconductor structure,the spacings between the adjacent leading wire posts 5 may be the same.In addition, referring to FIG. 17 , the spacings between the adjacentleading wire posts 5 may be adjusted according to different areas of thedirectly facing regions, so as to balance the parasitic capacitanceamong different leading wire posts 5.

In some embodiments, referring to FIG. 14 -FIG. 17 , the width of theleading wire post 5 in the first direction X is equal to the width ofthe memory cell group TC0, so that it contributes to unifyingcharacteristic sizes of different structures, so as to simplify theproduction process. In some other embodiments, referring to FIG. 18 ,the width of the leading wire post 5 in the first direction X is greaterthan the width of the memory cell group TC0, so that it contributes toincreasing the contact region between the leading wire post 5 and thehorizontal signal line 3 of the corresponding layer, so as to reduce thecontact resistance.

In addition, the width of the leading wire post 5 in the first directionX may be greater than or equal to the spacing between adjacent memorycell groups TC0. Such arrangement contributes to increasing the contactregion between the leading wire post 5 and the horizontal signal line 3of the corresponding layer, so as to reduce the contact resistance.

In addition, referring to FIG. 18 , the width of the leading wire post 5in the first direction X is greater than the width of the leading wirepost 5 in the third direction Y. It is to be noted that the horizontalsignal line 3 has a long length in the first direction X, and thus theleading wire post 5 has an enough accommodation space in the firstdirection X. In order to improve the utilization ratio of asemiconductor space while increasing the cross sectional areas of theleading wire posts 5, the leading wire posts 5 may be arranged in thefirst direction X and the third direction Y with certain widthdifferences.

In example 2, referring to FIG. 19 -FIG. 20 , the leading wire post 5and the memory cell TC are located on the same side of the horizontalsignal line 3. That is, the leading wire post 5 is located betweenadjacent memory cell groups TC0. Therefore, it contributes to makingfull use of the space position in the stacked structure, therebyimproving the space utilization ratio.

Continuously referring to FIG. 19 -FIG. 20 , in order to reduce theparasitic capacitance between adjacent leading wire posts 5, theadjacent leading wire posts 5 may be spaced by at least two memory cellgroups TC0. In addition, referring to FIG. 19 , in order to increase theuniformity of the semiconductor structure, the number of the memory cellgroups TC0 spaced between the adjacent leading wire posts 5 may be thesame. In addition, referring to FIG. 20 , the number of the memory cellgroups TC0 spaced between the adjacent leading wire posts 5 may beadjusted according to different areas of the directly facing regions, soas to balance the parasitic capacitance among different leading wireposts 5.

In some embodiments, referring to FIG. 19 -FIG. 20 , the width of theleading wire post 5 in the third direction Y is greater than the widthof the leading wire post 5 in the first direction X. Therefore, not onlycan the spacing between the adjacent memory cell groups TC0 be reduced,so as to reduce the area occupied by the stacked structure on thesurface of the substrate, but also the cross sectional area of theleading wire post 5 can be increased, so as to reduce the contactresistance of the leading wire post 5. In some other embodiments, thewidth of the leading wire post 5 in the third direction Y may be equalto the width of the leading wire post 5 in the first direction X.

It is to be noted that the example 1 and example 2 may be combined, thatis, part of leading wire posts 5 is located on one side of thehorizontal signal line 3 and the other part of leading wire posts 5 islocated on the other side of the horizontal signal line 3.

In some embodiments, referring to FIG. 14 -FIG. 20 , there is one memorycell in each layer of the memory cell group TC0. In another embodiment,referring to FIG. 21 -FIG. 22 , there are two memory cells TC in eachlayer of the memory cell group TC0, and two memory cells TC arerespectively located in two opposite sides of the horizontal signal line3 arranged in the third direction Y. Since the number of the memorycells TC in the memory cell group TC0 is increased, the storage capacityof the semiconductor is correspondingly enhanced.

In some embodiments, referring to FIG. 21 , part of leading wire posts 5may be located between adjacent memory cells TC0 of a stacked structure,and part of leading wire posts 5 may be located between adjacent memorycells TC0 of another stacked structure. That is, a plurality of leadingwire posts 5 are located on two different sides of the horizontal signalline 3. For example, adjacent leading wire posts 5 are located ondifferent sides of the horizontal signal line 3. In other words, twoadjacent leading wire posts 5 are staggered in the first direction X, sothat the parasitic capacitance may be reduced.

In some other embodiments, referring to FIG. 22 , all the leading wireposts 5 are located on the same side of the horizontal signal line 3, sothat it contributes to improving the uniformity of the arrangement modeof the leading wire posts 5, so as to simplify the manufacturing processof the semiconductor.

It is to be noted that in some embodiments, one leading wire post 5 mayonly be used for leading out one horizontal signal line 3 of one stackedstructure. In some other embodiments, one leading wire post 5 may beshared by two stacked structures. Specifically, referring to FIG. 23-FIG. 24 , FIG. 23 is a top view, and FIG. 24 is a section view of FIG.23 in the third direction Y. The horizontal signal lines 3 of twoadjacent stacked structures are arranged opposite. The leading wire post5 is located between the horizontal signal lines 3 of the adjacentstacked structures, and the horizontal signal lines 3 of the same layerof the adjacent stacked structures are electrically connected through atleast one leading wire post 5. Since the leading wire post 5 may beshared by two stacked structures, the number of the leading wire posts 5may be decreased, so that it contributes to reducing the volume of thesemiconductor structure.

It is to be noted that although the horizontal signal lines 3 of twostacked structures are electrically connected, the memory cells TCcorresponding to the horizontal signal lines 3 are still controlled bydifferent WLs, and therefore, the memory cells TC of the two stackedstructures can still be controlled independently.

In a case that the horizontal signal lines 3 are WLs, the horizontalsignal lines 3 and the leading wire posts mainly have the followingseveral position relationships.

First, it is to be noted that there are various position relationshipsbetween the WL and the channel region 22. For example, the WL may coverthe entire channel region 22. Alternatively, the WL(s) may be contactedwith the top surface and/or the bottom surface of the channel region 22.If the WL covers the entire channel region 22, the area of the side wallof the WL is larger. Since the side wall of the WL is contacted with aside wall of the leading wire post 5, the larger area of the side wallof the WL is beneficial to increasing the contact region between the WLand the leading wire post 5, thereby reducing the contact resistance. Ina case that the WLs are located on the top surface and the bottomsurface of the channel region 22, in order to increase the contactregions, the leading wire posts 5 may be simultaneously contacted withthe WLs on the top surface and the bottom surface of the channel region22.

In some other embodiments, referring to FIG. 25 -FIG. 27 , all theleading wire posts 5 are located on the same side of the horizontalsignal line 3, so that it contributes to improving the uniformity of thearrangement of the leading wire posts 5, so as to simplify themanufacturing process of the semiconductor. Exemplarily, referring toFIG. 25 , all the leading wire posts 5 are located on the side of thehorizontal signal line 3 close to the first source/drain doped region211. Referring to FIG. 26 -FIG. 27 , all the leading wire posts 5 arelocated on the side of the horizontal signal line 3 close to the secondsource/drain doped region 212.

Referring to FIG. 25 -FIG. 27 , in order to reduce the parasiticcapacitance, the adjacent leading wire posts 5 may be spaced at least bytwo memory cell groups TC0. In addition, referring to FIG. 25 and FIG.26 , in order to increase the uniformity of the semiconductor structure,the number of memory cell groups TC0 between the adjacent leading wireposts 5 may be the same. Alternatively, referring to FIG. 27 , thenumber of the memory cell groups TC0 spaced between the adjacent leadingwire posts 5 may be adjusted according to different areas of thedirectly facing regions, so as to balance the parasitic capacitanceamong different leading wire posts 5.

In some other embodiments, referring to FIG. 28 , part of leading wireposts 5 may be located on one side of the horizontal signal line 3 andpart of leading wire posts 5 may be located on the other side of thehorizontal signal line 3. Exemplarily, adjacent leading wire posts 5 arelocated on different sides of the horizontal signal line 3, that is, theleading wire posts 5 may be staggered in the first direction X, so thatthe parasitic capacitance is reduced.

In an embodiment of the disclosure, the plurality of leading wire posts5 and the plurality of horizontal signal lines are arranged along thethird direction Y, and the leading wire posts 5 are connected to thehorizontal signal lines 3. That is, an edge of the orthographicprojection of the leading wire posts 5 on the surface of the substrateis in contact with an edge of the orthographic projection of thehorizontal signal line 3 on the surface of the substrate. Since theleading wire posts 5 are directly connected to the horizontal signallines 3, the numbers of the connection layers and the staircases may bedecreased, thereby improving the integration level of the semiconductorstructure.

As shown in FIG. 29 -FIG. 44 , another embodiment of the disclosureprovides a semiconductor structure. The semiconductor structure issubstantially same as the semiconductor structure in the aforementionedembodiments. The main difference lies in that orthographic projectionsof the plurality of leading wire posts 5 of the semiconductor structureon the surface of the substrate are at least partially overlapped withorthographic projections of the horizontal signal lines 3 on the surfaceof the substrate. Parts of the semiconductor structure same as orsimilar to the semiconductor structure in the aforementioned embodimentsrefer to detailed description in the aforementioned embodiments, whichis not elaborated herein.

The semiconductor structure includes: a substrate (not shown in thedrawings), on which a stacked structure is provided, and the stackedstructure includes a plurality of memory cell groups TC0 arranged in thefirst direction X, and each of the memory cell groups TC0 includesmultiple layers of memory cells TC arranged in the second direction Z,and the stacked structure further includes a plurality of horizontalsignal lines 3 arranged in the second direction Z, and each of thehorizontal signal lines 3 is contacted with one layer of the memorycells TC; a plurality of leading wire posts 5 arranged in the firstdirection X and extending along the second direction Z, and orthographicprojections of the plurality of leading wire posts 5 on the surface ofthe substrate are at least partially overlapped with orthographicprojections of the horizontal signal lines 3 on the surface of thesubstrate, and the leading wire posts 5 are connected to the horizontalsignal lines 3.

That is, the leading wire posts 5 are directly connected to thehorizontal signal lines 3 in an alternative manner by at least utilizingthe space positions of part of the horizontal signal lines 3, so that itcontributes to reducing the number of staircases or it is no longer toarrange a staircase area independently, thereby improving theintegration level of the semiconductor structure.

The semiconductor structure will be described below in detail incombination with the drawings.

Referring to FIG. 29 -FIG. 37 , the leading wire post 5 is located onthe top surface of the horizontal signal line 3 of the correspondinglayer, and the bottom surface of the leading wire post 5 is contactedwith the top surface of the horizontal signal line 3 of thecorresponding layer. In some other embodiments, the bottom of theleading wire post 5 may be embedded into the horizontal signal line 3 ofthe corresponding layer; alternatively, the bottom of the leading wirepost 5 may penetrate through the horizontal signal line 3 of thecorresponding layer, that is, the side wall of the leading wire post 5may also be contacted with the horizontal signal line 3 of thecorresponding layer.

Referring to FIG. 29 -FIG. 30 , FIG. 32 , FIG. 34 and FIG. 36 , at leastone leading wire post 5 penetrates through at least one horizontalsignal line 3, that is, at least one of the leading wire posts 5 isconnected to the horizontal signal line 3 of the non-top layer. It is tobe noted that the leading wire post 5 connected to the horizontal signalline 3 of the non-top layer needs to occupy, besides the space positionof the horizontal signal line 3 of the corresponding layer, the spaceposition of the horizontal signal line 3 above the corresponding layer.Therefore, the leading wire post 5 will penetrate through the horizontalsignal line 3 located above the corresponding layer. Referring to FIG.31 , with respect to the leading wire post 5 connected to the horizontalsignal line 3 of the top layer, the leading wire post 5 does not need topenetrate through the horizontal signal lines 3 out of the correspondinglayer.

It is to be noted that the leading wire post 5 penetrates through thehorizontal signal line 3 located above the corresponding layer, but thehorizontal signal line 3 above the corresponding layer is not truncatedcompletely.

Specifically, referring to FIG. 29 -FIG. 44 , the horizontal signal line3 includes a contact region 31 and an exposed region 32 arranged in thethird direction Y; the leading wire post 5 is connected to the contactregion 31, and the exposed region 32 is exposed; and the third directionY is perpendicular to the second direction Z and parallel to the surfaceof the substrate. That is to say, the leading wire post 5 is contactedwith the contact region 31 of the horizontal signal line 3 of thecorresponding layer and penetrates through the contact region 31 of thehorizontal signal line 3 located above the corresponding layer, and theexposed regions 32 of all the horizontal signal lines 3 are exposed.Although the horizontal signal line 3 above the corresponding layer ispenetrated, the horizontal signal line 3 will not be completelytruncated since the exposed regions 32 are reserved, and the horizontalsignal line 3 may still be contacted with the memory cell TC of the samelayer.

In some embodiments, referring to FIG. 32 -FIG. 33 , FIG. 33 illustratesa partial enlarged drawing of the horizontal signal line 3 of thecorresponding layer and the leading wire post 5 in FIG. 32 . The exposedregions 32 are located on two opposite sides of the contact region 31.The orthographic projection of the leading wire post 5 on the surface ofthe substrate is overlapped with the orthographic projection of thecontact region 31 on the surface of the substrate. That is to say, thecontact region 31 is located in a center position of the horizontalsignal line 3, the leading wire post 5 is connected to the center of thehorizontal signal line 3 of the corresponding layer and penetratesthrough the center of the horizontal signal line 3 located above thecorresponding layer, the exposed regions 32 of the horizontal signalline 3 are not truncated, and the horizontal signal line 3 may still becontacted with the memory cells TC of the same layer.

In some other embodiments, referring to FIG. 34 -FIG. 38 , FIG. 35illustrates a partial enlarged drawing of the horizontal signal line 3of the corresponding layer and the leading wire post 5 in FIG. 34 , FIG.37 illustrates a partial enlarged drawing of the horizontal signal line3 of the corresponding layer and the leading wire post 5 in FIG. 36 ,and FIG. 38 is a top view of the semiconductor structure shown in FIG.36 . The horizontal signal line 3 has two opposite sides arranged in thethird direction Y, the exposed region 32 is located on one of the twoopposite sides, and the contact region 31 is located on the other of thetwo opposite sides. That is, the leading wire post 5 is contacted withone side of the horizontal signal line 3 of the corresponding layer andthe other side of the horizontal signal line 3 is exposed, the leadingwire post 5 penetrates through one side of the horizontal signal line 3above the corresponding layer, and the other side of the horizontalsignal line 3 above the corresponding layer is not penetrated.

In an example, referring to FIG. 34 -FIG. 35 , the orthographicprojection of the leading wire post 5 on the surface of the substrate isoverlapped with the orthographic projection of the exposed region 32 onthe surface of the substrate. That is, in the direction parallel to thesubstrate, the leading wire post 5 utilizes the space position of thehorizontal signal line 3 and does not exceed the horizontal signal line3, so that it contributes to improving the compact degree between theleading wire post 5 and the horizontal signal line 3, so as to improvethe space utilization ratio.

In another example, referring to FIG. 36 -FIG. 38 , the leading wirepost 5 is protruded relative to the contact region 31. That is, theleading wire post 5 is protruded relative to one side of the horizontalsignal line 3. That is to say, only part of the bottom surface of theleading wire post 5 is in contact connection with the contact region 31.Protruding arrangement may reduce the area of the horizontal signal line3 above the corresponding layer penetrated by the leading wire post 5,so that the resistance of the horizontal signal line 3 above thecorresponding layer is reduced. Meanwhile, it may further guarantee thatthe leading wire post 5 has a large cross sectional area, so that theresistance of the leading wire post 5 is reduced.

It is to be noted that in some embodiments, the horizontal signal line 3may be strip-like, that is, the orthographic projection of thehorizontal signal line 3 on the surface of the substrate is rectangular.In some other embodiments, the horizontal signal line 3 may include amain body portion and a protrusion portion connected with each other.The main body portion is strip-like, and the protrusion portion may bein shapes such as square or zigzag, that is, the length of theprotrusion portion in the first direction X is smaller than the lengthof the main body portion in the first direction X. The main body portionand the protrusion portion may be arranged in the third direction Y. Themain body portion is contacted with the memory cell group TC0, and theprotrusion portion is contacted with the leading wire post 5.Exemplarily, the bottom surface of the leading wire post 5 is contactedwith the top surface of the protrusion portion of the correspondinglayer, and therefore, the leading wire post 5 may not need to penetratethrough the main body portion above the corresponding layer, so that itcontributes to reducing the resistance of the horizontal signal line 3above the corresponding layer.

Referring to FIG. 29 -FIG. 30 , the memory cell TC includes the channelregion 22 and source/drain doped regions 21 arranged in the thirddirection Y, and the source/drain doped regions 21 are located on twosides of the channel region 22. That is, the memory cell TC at leastincludes the transistor T. In some other embodiments, the memory cell TCmay further include the capacitor C, and the transistor T and thecapacitor C are arranged in the third direction Y. The source/draindoped regions 21 may include the first source/drain doped region 211 andthe second source/drain doped region 212, the first source/drain dopedregion 211 may be contacted with the BL, and the second source/draindoped region 212 may be located on the side of the channel region 22away from the first source/drain doped region 211.

The stacked structure also includes perpendicular signal lines 4extending along the second direction Z and connected to multiple layersof memory cells TC in the same memory cell group TC0. One of thehorizontal signal line 3 and the perpendicular signal line 4 is a BL,and the other of the horizontal signal line 3 and the perpendicularsignal line 4 is a WL. The BL is contacted with the source/drain dopedregion 21, and the WL is contacted with the channel region 22.

Position relationships between the horizontal signal lines 3 and theleading wire posts 5 will be described below in detail in twosituations: the horizontal signal lines are BLs and the horizontalsignal lines are WLs.

In a case that the horizontal signal lines 3 are BLs, the horizontalsignal lines 3 and the leading wire posts 5 mainly have the followingseveral position relationships.

In example 1, referring to FIG. 38 -FIG. 39 , the leading wire post 5directly faces the memory cell group TC0 in the third direction Y.Therefore, it contributes to improving the uniformity of positionarrangement.

In example 2, referring to FIG. 40 , the leading wire posts 5 and thememory cell groups TC are arranged alternatively in the first directionX. That is, the leading wire post may directly face the space betweenadjacent memory cell groups TC0.

In example 3, referring to FIG. 41 , the leading wire post 5 is arrangedsimultaneously opposite the memory cell group TC0 and the space betweenthe adjacent memory cell groups TC0.

It is to be noted that in the case that the horizontal signal line 3 isthe BL, in order to prevent the leading wire post 5 from cutting off theconnection between the horizontal signal line 3 above the correspondinglayer and the memory cell TC, the exposed region 32 may be located onthe side close to the memory cell TC, and the contact region 31 may belocated on the side away from the memory cell TC; alternatively, theexposed regions 32 may be located on two opposite sides of the contactregion 31.

In some embodiment, referring to FIG. 42 , there are two memory cells TCin each layer of the memory cell group TC0, and the two memory cells TCare respectively located in two opposite sides of the horizontal signalline 3 arranged in the third direction Y. In such case, one leading wirepost 5 leads out more memory cells TC through the horizontal signal line3, thereby facilitating to improve the integration level of thesemiconductor structure.

In a case that the horizontal signal lines 3 are the WLs, the horizontalsignal lines 3 and the leading wire posts 5 mainly have the followingseveral position relationships.

In example 1, referring to FIG. 43 , the leading wire post 5 is locatedbetween adjacent memory cell groups TC0, that is, the leading wire post5 and the channel region 22 are staggered, so that the leading wire post5 may be prevented from truncating the memory cell TC located above thecorresponding layer, thereby reducing the number of the invalid memorycells TC.

In example 2, referring to FIG. 44 , the orthographic projection of theleading wire post 5 on the surface of the substrate is overlapped withthe orthographic projection of the channel region 22 on the surface ofthe substrate. That is, the leading wire post 5 may lead out thehorizontal signal line 3 by utilizing the position of the channel region22, so that it contributes to reducing the spacing between adjacentmemory cell groups TC0, so as to improve the compact degree of thememory cell groups TC0, thereby reducing the failure rate of thesemiconductor structure.

In another embodiment of the disclosure, edges of the orthographicprojection of the leading wire posts 5 on the surface of the substrateand the orthographic projection of the horizontal signal line 3 on thesurface of the substrate are overlapped. That is, the leading wire post5 may be directly connected to the horizontal signal line 3 by utilizingthe space of the horizontal signal line 3 itself, and thus the numbersof the connection layers and the staircases may be decreased, therebyimproving the integration level of the semiconductor structure.

As shown in FIG. 45 -FIG. 46 , another embodiment of the disclosureprovides a method for manufacturing a semiconductor structure. It is tobe noted that in order to conveniently describe and clearly illustrateoperations of the method for manufacturing a semiconductor structure,FIG. 45 -FIG. 56 all are partial schematic structural diagrams of thesemiconductor structure. The method for manufacturing a semiconductorstructure provided by an embodiment of the disclosure will be describedbelow in detail in combination with the drawings.

A substrate is provided. A stacked structure is formed on the substrate,the stacked structure includes a plurality of memory cell groups TC0arranged in a first direction X, and each of the memory cell groups TC0includes multiple layers of memory cells TC arranged in a seconddirection Z. The stacked structure further includes a plurality ofhorizontal signal lines 3 arranged in the second direction Z, and eachof the horizontal signal lines 3 is contacted with one layer of thememory cells TC.

Exemplarily, the memory cell TC may include the transistor T and thecapacitor C. Specifically, the operation of forming the transistor T mayinclude the following operations. Multiple spaced active layers areformed, and each of the active layers includes a plurality of activestructures. The active structure is doped, so as to form thesource/drain doped regions 21 and the channel region 22. A gatedielectric layer 6 is formed on the surface of the channel region 22.That is to say, the memory cell TC includes the channel region 22 andthe source/drain doped regions 21 arranged in the third direction Y, andthe source/drain doped regions 21 are located on two sides of thechannel region 22; and the third direction Y is parallel to the surfaceof the substrate. In addition, it is necessary to form the insulatinglayer 12 between the transistors T of adjacent layers, so as to isolatethe adjacent transistors T. The operation of forming the capacitor C mayinclude the following operations. A capacitor supporting layer and acapacitor hole located in the capacitor supporting layer are formed. Alower electrode is formed on the inner wall of the capacitor hole, acapacitor dielectric layer 6 is formed on the surface of the lowerelectrode, and an upper electrode is formed on the surface of thecapacitor dielectric layer 6. The lower electrode, the capacitordielectric layer 6 and the upper electrode form the capacitor C.

A plurality of leading wire posts 5 arranged in the first direction Xare formed. The plurality of leading wire posts 5 and the plurality ofhorizontal signal lines are arranged along the third direction Y, andthe leading wire posts 5 are connected to the horizontal signal lines 3.

The method for forming the leading wire post 5 will be described belowin detail.

It is to be noted first that the plurality of horizontal signal lines 3include the first to N^(th) horizontal signal lines successivelyarranged in the second direction Z, N being a positive integer greaterthan 1. The first horizontal signal line is located in the top layer,and the N^(th) horizontal signal line is located in the bottom layer.

Referring to FIG. 45 -FIG. 56 , the through hole 8 is formed. Thethrough hole 8 includes the first through hole to the N^(th) throughhole, a side wall of the first horizontal signal line is exposed by thefirst through hole, and side walls of the first horizontal signal lineto the N^(th) horizontal signal line are exposed by the N^(th) throughhole.

Taking the horizontal signal line 3 being a BL as an example, theoperations of forming the through hole 8 will be described in detail.

Referring to FIG. 45 -FIG. 46 , an isolation structure is formed on theside wall of the horizontal signal line 3. In some embodiments, theisolation structure may include an etching barrier layer 13 and anisolation layer 14 arranged alternately. The isolation layer 14 and thehorizontal signal line 3 are arranged in the same layer, and the etchingbarrier layer 13 is arranged directly opposite the insulating layer 12between the adjacent horizontal signal lines 3 (referring to FIG. 10 ).In some other embodiments, the isolation structure may only include theisolation layer 14, and the isolation layer 14 covers the side walls ofthe horizontal signal line 3 and the insulating layer 12.

Continuously referring to FIG. 45 -FIG. 46 , a mask layer 71 is formed.The mask layer 71 has N openings 72, N being a positive integer greaterthan 1. The openings 72 are located on one side of the horizontal signalline 3. Exemplarily, the mask layer 71 may be a photoresist layer, andthe photoresist layer is photoetched to form the openings 72.Alternatively, the mask layer 71 may be a hard mask layer 71 and aphotoresist layer arranged in a stacked manner, and after thephotoresist layer is photoetched, the hard mask layer 71 is etched, soas to form the openings 72.

Referring to FIG. 47 -FIG. 48 , the isolation layer 14 of the top layeris etched along the openings 72 until the etching barrier layer 13 ofthe top layer is exposed, so as to form a plurality of first sub-throughholes 811. The first sub-through holes 811 expose side walls of thefirst horizontal signal line, and one of the first sub-through holes 811serves as the first through hole 81.

Referring to FIG. 49 -FIG. 50 , a sacrificial layer 73 filling the firstsub-through holes 811 is formed. Exemplarily, a material with a lowdielectric constant, such as silicon oxide, is deposited in the firstsub-through holes 811 to serve as the sacrificial layer 73.

Continuously referring to FIG. 49 -FIG. 50 , the mask layer 71 ispatterned to enable the mask layer 71 to have (N−1) openings 72.Specifically, the photoresist layer may be spin-coated again andphotoetched, to form the openings 72.

Referring to FIG. 51 -FIG. 52 , the sacrificial layer 73 and theisolation layer 14 of the second layer are etched along the openings 72to form (N−1) second sub-through holes 821. One of the secondsub-through holes 821 serves as a second through hole 82.

Referring to FIG. 53 -FIG. 54 , the operations of forming thesacrificial layer 73, patterning the mask layer 71 and etching arerepeated until the side wall of the N^(th) horizontal signal line 3 isexposed, that is, the top surface of the N^(th) etching barrier layer isexposed.

Based on FIG. 49 -FIG. 54 , the through holes 8 may be formed, and thethrough holes 8 include the first through hole 8 to the N^(th) throughhole 8. Exemplarily, referring to FIG. 53 -FIG. 54 , the first throughhole 81, the second through hole 82, the third through hole 84, thefourth through hole 84 and the fifth through hole 85 may be formed. Itis to be noted that in the first direction X, depths of the firstthrough hole 81, the second through hole 82, the third through hole 83,the fourth through hole 84 and the fifth through hole 85 successivelyarranged are increased in sequence. In other embodiments, in the firstdirection X, depths of the first through hole 81, the second throughhole 82, the third through hole 83, the fourth through hole 84 and thefifth through hole 85 successively arranged may not be progressivelyincreased or decreased, but the through holes are formed alternativelyin depth, so as to avoid too large parasitic capacitance between theleading wire posts 5 with large depths among the subsequently formedleading wire posts 5.

It is to be noted that in a case that the horizontal signal line 3 isthe WL, the operations of forming the through holes 8 are similar to theaforementioned operations, and the main difference lies in that theinsulating layer 12 between the adjacent memory cell groups TC0 isetched to form the through holes 8. Other operations about forming themask layer 71 and the sacrificial layer 73 may refer to the abovedetailed description.

Referring to FIG. 55 -FIG. 56 , the first contact portion to the N^(th)contact portion are respectively formed at the bottoms of the firstthrough hole 81 to the N^(th) through hole, the first contact portion tothe N^(th) contact portion are respectively arranged in the same layersas the first horizontal signal line to the N^(th) horizontal signal line3, and the contact portion 51 covers the side wall of the firsthorizontal signal 3 of the corresponding layer.

Continuously referring to FIG. 55 -FIG. 56 , after the contact portion51 is formed, the dielectric layer 6 is formed on the side wall of thethrough hole 8. Exemplarily, an initial dielectric layer is formed onthe side wall of the through hole 8 and the surface of the contactportion 51 through a chemical vapor deposition process. The initialdielectric layer on the surface of the contact portion 51 is removed,and the initial dielectric layer located on the side wall of the throughhole 8 serves as the dielectric layer 6.

Continuously referring to FIG. 55 -FIG. 56 , an extension portion 52filling the through hole 8 is formed, and the contact portion 51 and theextension portion 52 form the leading wire post 5. Exemplarily, metalssuch as copper, aluminum, titanium or tungsten are deposited in thethrough hole 8 as the leading wire post 5.

It is to be noted that the abovementioned method for forming the leadingwire post 5 is merely exemplary description but is not limited thereto.The method for forming the leading wire post 5 may be adjusted accordingto a specific structure of the leading wire post 5.

As shown in FIG. 57 -FIG. 60 , another embodiment of the disclosureprovides a method for manufacturing a semiconductor structure. Themethod for manufacturing a semiconductor structure is substantially sameas the aforementioned method for manufacturing a semiconductorstructure, and same or similar parts refer to detailed description inthe aforementioned embodiments. In order to conveniently describe andclearly illustrate operations of the method for manufacturing asemiconductor, FIG. 57 -FIG. 60 all are partial schematic structuraldiagrams of the semiconductor structure. The method for manufacturing asemiconductor structure will be described below in detail in combinationwith the drawings.

A substrate is provided. A stacked structure is formed on the substrate,the stacked structure includes a plurality of memory cell groups TC0arranged in a first direction X, and each of the memory cell groups TC0includes multiple layers of memory cells TC arranged in a seconddirection Z. The stacked structure further includes a plurality ofhorizontal signal lines 3 arranged in the second direction Z, and eachof the horizontal signal lines 3 is contacted with one layer of thememory cells TC.

The method about forming the stacked structure may refer to detaileddescription of the aforementioned embodiments.

Referring to FIG. 57 -FIG. 60 , the plurality of leading wire posts 5arranged in the first direction and X and extending along the seconddirection Z are formed. Orthographic projections of the plurality ofleading wire posts 5 on the surface of the substrate are at leastpartially overlapped with orthographic projections of the horizontalsignal lines 3 on the surface of the substrate, and the leading wireposts 5 are connected to the horizontal signal lines 3.

The method for manufacturing the leading wire posts 5 will be describedbelow in detail.

It is to be noted first that the plurality of horizontal signal lines 3include the first to N^(th) horizontal signal lines successivelyarranged in the second direction Z, N being a positive integer greaterthan 1. The first horizontal signal line is located in the top layer,and the N^(th) horizontal signal line is located in the bottom layer.

Referring to FIG. 57 -FIG. 58 , the through holes 8 are formed, and thethrough holes 8 include the first through hole 81 to the N^(th) throughhole. The top surface of the first horizontal signal line is exposed bythe first through hole 81; the N^(th) through hole penetrates throughthe first horizontal signal line to the (N−1)^(th) horizontal signalline, and exposes the top surface of the N^(th) horizontal signal line.

The operations of forming the through hole 8 are substantially same asthe operations in the aforementioned embodiments, and the maindifference lies in that the through hole 8 penetrates through one ormore horizontal signal lines 3, and therefore, it is necessary to etchthe one or more horizontal signal lines 3. In addition, in a case thatthe leading wire post 5 utilizes the position of the memory cell groupTC0, it is further necessary to etch the channel region 22 and theinsulating layer 12 located between memory cells TC of the upper layerand memory cells TC of the lower layer when the through hole 8 isformed; and in a case that the leading wire post 5 utilizes the positionbetween the adjacent memory cell groups TC0, it is further necessary toetch the insulating layer 12 between adjacent memory cells TC when thethrough hole 8 is formed. Other operations about forming the mask layer71 and the sacrificial layer 73 may refer to detailed description of theaforementioned embodiments.

Referring to FIG. 59 -FIG. 60 , the dielectric layer 6 is formed on theside wall of the through hole 8. Specifically, an initial dielectriclayer is formed on the inner walls of the through hole 8. The initialdielectric layer located on the bottom wall of the through hole 8 isremoved to expose the horizontal signal line 3 of the correspondinglayer, and the initial dielectric layer located on the side wall of thethrough hole 8 serves as the dielectric layer 6. The leading wire post 5filling the through hole 8 is formed, and the bottom surface of theleading wire post 5 is electrically connected to the horizontal signalline 3.

In the embodiments of the disclosure, the horizontal signal line 3 isetched to form the through hole 8, and the dielectric layer 6 and theleading wire post 5 filling the through hole 8 are formed. Therefore,the leading wire post 5 may be electrically connected to the horizontalsignal line 3 directly by utilizing the spatial position of thehorizontal signal line 3, so that the number of the staircases may bereduced or the independent staircase area is not formed, therebyimproving the integration level of the semiconductor structure.

The embodiments of the disclosure further provide a memory chip,including the semiconductor structure provided by the aforementionedembodiments.

The memory chip is a memory part for storing programs and various datainformation. Exemplarily, the memory chip may be a random access memorychip or a read-only memory chip. For example, the random access memorychip may include a Dynamic Random Access Memory (DRAM) or a StaticRandom Access Memory (SRAM). The integration level of the aforementionedsemiconductor structure is high, which contributes to realizingmicrominiaturization of the memory chip.

The embodiments of the disclosure further provide an electronic device,including the memory chip provided by the aforementioned embodiments.

Exemplarily, the electronic device may be a device such as a television,a computer, a mobile phone or a tablet computer. The electronic devicemay include a circuit board and a package structure, and the memory chipmay be welded to the circuit board and protected by the packagestructure. In addition, the electronic device may further include apower supply for providing an operating voltage to the memory chip.

In the description of the specification, the description with referenceto the terms “some embodiments”, “exemplarily”, and the like means thatspecific features, structures, materials, or features described incombination with the embodiments or examples are included in at leastone embodiment or example of the disclosure. In the description,schematic expressions of the terms do not have to mean same embodimentsor exemplary embodiments. Furthermore, specific features, structures,materials or characteristics described can be combined in any one ormore embodiments or exemplary embodiments in proper manners. Inaddition, those skilled in the art can integrate or combine, withoutmutual contradiction, different embodiments or exemplary embodiments andintegrate or combine features of different embodiments or exemplaryembodiments described in the description.

Although the embodiments of the disclosure have been shown and describedabove, it can be understood that the embodiments are exemplary andshould not be construed as limitation to the disclosure. Those ofordinary skill in the art can make changes, modifications, replacementsand variations to the embodiments within the scope of the presentdisclosure. Any variations or and modifications made followed by claimsand description of the disclosure shall fall within the scope of thedisclosure.

1. A semiconductor structure, comprising: a substrate, on which astacked structure is provided, wherein the stacked structure comprises aplurality of memory cell groups arranged in a first direction, each ofthe memory cell groups comprising multiple layers of memory cellsarranged in a second direction, and the stacked structure furthercomprises a plurality of horizontal signal lines arranged in the seconddirection, each of the horizontal signal lines being in contact with onelayer of the memory cells; and a plurality of leading wire postsarranged in the first direction, wherein the plurality of leading wireposts and the plurality of horizontal signal lines are arranged along athird direction, and the leading wire posts are connected to thehorizontal signal lines.
 2. The semiconductor structure according toclaim 1, wherein each horizontal signal line is at least connected toone of the leading wire posts, and the plurality of horizontal signallines are connected to the plurality of leading wire posts in one-to-onecorrespondence.
 3. The semiconductor structure according to claim 1,wherein the leading wire posts connected to different horizontal signallines are different in length in the second direction, and bottoms ofthe leading wire posts are contacted with the horizontal signal lines.4. The semiconductor structure according to claim 1, wherein adjacentleading wire posts are arranged at an equal spacing in the firstdirection; or, a spacing between the adjacent leading wire posts is inproportion to an area of a directly facing region between the adjacentleading wire posts.
 5. The semiconductor structure according to claim 1,wherein the stacked structure further comprises: multiple etchingbarrier layers arranged in the second direction, each etching barrierlayer being contacted with a bottom surface of at least one of theleading wire posts; or, the stacked structure further comprises: adielectric layer, at least located on a side wall of a leading wire postfacing a horizontal signal line, a lower surface of the dielectric layerbeing higher than the horizontal signal line connected to the leadingwire post.
 6. The semiconductor structure according to claim 1, whereineach memory cell comprises a channel region and source/drain dopedregions arranged in the third direction, the source/drain doped regionsbeing located on two sides of the channel region.
 7. The semiconductorstructure according to claim 6, wherein the horizontal signal line is abit line, the bit line being contacted with the source/drain dopedregions.
 8. The semiconductor structure according to claim 7, whereinthe leading wire post and the memory cell are respectively located ontwo opposite sides of the horizontal signal line arranged in the thirddirection.
 9. The semiconductor structure according to claim 8, whereina width of the leading wire post in the first direction is greater thanor equal to that of the memory cell group; and/or the width of theleading wire post in the first direction is greater than or equal to aspacing between adjacent memory cell groups; and/or the width of theleading wire post in the first direction is greater than that of theleading wire post in the third direction; or, wherein the leading wireposts and the memory cell groups are directly opposite in the thirddirection; or the leading wire posts and the memory cell groups arearranged alternatively in the first direction.
 10. The semiconductorstructure according to claim 7, wherein the leading wire post and thememory cell are located on a same side of the horizontal signal line,and a width of the leading wire post in the third direction is greaterthan that of the leading wire post in the first direction.
 11. Thesemiconductor structure according to claim 7, wherein horizontal signallines of two adjacent stacked structures are arranged opposite, aleading wire post is located between horizontal signal lines of theadjacent stacked structures, and horizontal signal lines of the samelayers of the adjacent stacked structures are electrically connectedthrough at least one of the leading wire posts.
 12. The semiconductorstructure according to claim 7, wherein each layer of memory cells inthe memory cell group comprises two memory cells, and the two memorycells are respectively located in two opposite sides of the horizontalsignal line arranged in the third direction, and wherein adjacentleading wire posts are located on different sides of the horizontalsignal line; or all the leading wire posts are located on the same sideof the horizontal signal line.
 13. The semiconductor structure accordingto claim 6, wherein the horizontal signal line is a word line, the wordline being contacted with the channel region, and wherein adjacentleading wire posts are located on different sides of the horizontalsignal line; or all the leading wire posts are located on the same sideof the horizontal signal line.
 14. A semiconductor structure,comprising: a substrate, on which a stacked structure is provided,wherein the stacked structure comprises a plurality of memory cellgroups arranged in a first direction, each of the memory cell groupscomprising multiple layers of memory cells arranged in a seconddirection, and the stacked structure further comprises a plurality ofhorizontal signal lines arranged in the second direction, each of thehorizontal signal lines being in contact with one layer of the memorycells; and a plurality of leading wire posts arranged in the firstdirection and extending along the second direction, wherein orthographicprojections of the plurality of leading wire posts on a surface of thesubstrate and orthographic projections of the horizontal signal lines onthe surface of the substrate are at least partially overlapped, and theleading wire posts are connected to the horizontal signal lines.
 15. Thesemiconductor structure according to claim 14, wherein at least one ofthe leading wire posts penetrates through at least one of the horizontalsignal lines.
 16. The semiconductor structure according to claim 14,wherein each horizontal signal line comprises a contact region and anexposed region arranged in a third direction, a leading wire post iscontacted with the contact region, and the third direction isperpendicular to the second direction and parallel to the surface of thesubstrate; and wherein the horizontal signal line has two opposite sidesarranged in the third direction, the exposed region is located on oneside of the two opposite sides, the contact region is located on theother side of the two opposite sides, and the leading wire post isprotruded relative to the contact region.
 17. The semiconductorstructure according to claim 14, wherein each memory cell comprises achannel region and source/drain doped regions arranged in a thirddirection, the source/drain doped regions being located on two sides ofthe channel region.
 18. The semiconductor structure according to claim17, wherein the horizontal signal line is a bit line, the bit line beingcontacted with the source/drain doped regions, and wherein the leadingwire posts and the memory cell groups are directly opposite in the thirddirection, or the leading wire posts and the memory cell groups arearranged alternatively in the first direction; or, wherein thehorizontal signal line is a word line, the word line being contactedwith the channel region, and wherein the leading wire post is locatedbetween adjacent memory cell groups, or an orthographic projection ofthe leading wire post on the surface of the substrate is overlapped withan orthographic projection of the channel region on the surface of thesubstrate.
 19. The semiconductor structure according to claim 14,wherein the horizontal signal line has two opposite sides arranged in athird direction, each layer of memory cells in the memory cell groupcomprises two memory cells, and the two memory cells are respectivelylocated in two opposite sides of the horizontal signal line arranged inthe third direction.
 20. A method for manufacturing a semiconductorstructure, comprising: providing a substrate; forming a stackedstructure on the substrate, wherein the stacked structure comprises aplurality of memory cell groups arranged in a first direction, each ofthe memory cell groups comprising multiple layers of memory cellsarranged in a second direction, and further comprises a plurality ofhorizontal signal lines arranged in the second direction, each of thehorizontal signal lines being in contact with one layer of the memorycells; and forming a plurality of leading wire posts arranged in thefirst direction, wherein the plurality of leading wire posts and theplurality of horizontal signal lines are arranged along a thirddirection, and the leading wire posts are connected to the horizontalsignal lines.